1. Field of the Invention
The present invention relates to a semiconductor device having an on-chip terminal with a voltage to be measured in a test.
2. Description of the Related Art
FIG. 5 shows a step-down circuit 10 included in a semiconductor device.
This circuit is used for providing an internal power supply voltage VII, obtained by stepping down an external power supply voltage VCC supplied to an external terminal of the circuit, to circuit blocks in the semiconductor device. For example, VCC=5.0 V and VII=3.3 V. A current flows from VCC to an NMOS transistor 11, and the source of the NMOS transistor 11 is the internal power supply voltage VII. The VII is lower than the gate voltage VG of the NMOS transistor 11 by the threshold voltage Vth thereof. Therefore, the gate voltage VG is controlled by a voltage control circuit 12 so as to be constant independently of variations of the voltage VCC and temperature.
In the voltage control circuit 12, a reference voltage Vref produced in a reference voltage generation circuit 14 is provided to the gate of an NMOS transistor 131 in a differential amplification circuit 13. The reference voltage Vref is almost constant independently of variations of the voltage VCC and temperature. The drain voltage of the NMOS transistor 131 is provided to the gate of a PMOS transistor 151 in an output buffer circuit 15 as the output of the differential amplification circuit 13. The voltage of a node N1 connected to the drain of the PMOS transistor 151 is the output VG of the voltage control circuit 12. The voltage VG is lowered by an NMOS transistor 152 in the output buffer circuit 15 by its threshold voltage Vth and provided to the gate of an NMOS transistor 132 in the differential amplification circuit 13. Therefore, the gate voltage of the NMOS transistor 132 is equal to the voltage VII to be controlled.
In the above described configuration, when VII falls down and then VII less than Vref, the gate voltage VG and the gate voltage of the NMOS transistor 132 fall as well. With the falls in the voltages, the gate voltage of the PMOS transistor 151 falls to decrease the internal resistance thereof, and the gate voltage VG together with the voltage VII rise. Contrary to this, when VII greater than Vref, the gate voltage of the PMOS transistor 151 rises to increase the internal resistance thereof, and the gate voltage VG together with the voltage VII fall. By such operation, the voltage VII follows the stabilized reference voltage Vref.
In order to measure the gate voltage VG prior to shipment of the semiconductor device, the node N1 is connected to a pad 16 formed on the semiconductor chip with the pad 16, the probe 18 connected through a cable 19 to a tester 17 is put into contact.
Since the voltage control circuit 12 is only required to control the gate voltage VG of the NMOS transistor 11, the current flowing through the output buffer circuit 15 can be small compared with the current flowing through the NMOS transistor 11 and thereby, low power consumption in the voltage control circuit 12 is realized by use of a larger resistance R1 of the output buffer circuit 15. On the other hand, although the internal resistance Rt of the tester 17 is comparatively large, the combined capacitance of the probe 18 and cable 19 is much larger than that of the node N1.
Hence, when the probe 18 of the tester 17 is put into contact with the pad 16, a change in the gate voltage VG cannot be detected correctly by the tester 17. If a circuit for diminishing an influence of the probe 18 and cable 19 of the tester 17 is incorporated in the step-down circuit 10, power consumption increases in normal operation by a user.
Accordingly, it is an object of the present invention to provide a semiconductor device, having an on-chip terminal with a voltage to be measured in a test, that makes it possible to more accurately measure the voltage of the terminal without increasing in power consumption in the normal use.
In the present invention, there is provided a semiconductor device comprising: an internal circuit having a node with a voltage to be measured in a test; an on-chip terminal; and a voltage follower circuit, having an input for receiving a voltage of the node, activated in response to activation of a test mode signal, for providing its output to the on-chip terminal.
With the present invention, the node voltage is indirectly measured through the voltage follower circuit and therefore, when the probe of a tester is put into contact with the on-chip terminal such as a pad, the influence of the capacitance of the probe is small, which in turn enables more accurate measurement of the node voltage of the internal circuit.
Further, since the voltage follower circuit is deactivated by deactivating the test mode signal in normal operation, increase in power consumption can be avoided even with the voltage follower circuit provided, otherwise a comparatively large current flows through the voltage follower circuit.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.